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19-2174; Rev 0; 10/01
Dual 10-Bit, 20Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs
General Description
The MAX1184 is a +3V, dual 10-bit analog-to-digital converter (ADC) featuring fully-differential wideband track-and-hold (T/H) inputs, driving two pipelined, 9stage ADCs. The MAX1184 is optimized for low-power, high-dynamic performance applications in imaging, instrumentation, and digital communication applications. This ADC operates from a single +2.7V to +3.6V supply, consuming only 105mW while delivering a typical signal-to-noise ratio (SNR) of 59.5dB at an input frequency of 7.5MHz and a sampling rate of 20Msps. The T/H driven input stages incorporate 400MHz (-3dB) input amplifiers. The converters may also be operated with single-ended inputs. In addition to low operating power, the MAX1184 features a 2.8mA sleep mode as well as a 1A power-down mode to conserve power during idle periods. An internal +2.048V precision bandgap reference sets the full-scale range of the ADC. A flexible reference structure allows the use of the internal or an externally derived reference, if desired for applications requiring increased accuracy or a different input voltage range. The MAX1184 features parallel, CMOS-compatible three-state outputs. The digital output format is set to two's complement or straight offset binary through a single control pin. The device provides for a separate output power supply of +1.7V to +3.6V for flexible interfacing. The MAX1184 is available in a 7mm x 7mm, 48pin TQFP package, and is specified for the extended industrial (-40C to +85C) temperature range. Pin-compatible higher speed versions of the MAX1184 are also available. Please refer to the MAX1180 data sheet for 105Msps, the MAX1181 data sheet for 80Msps, the MAX1182 data sheet for 65Msps, and the MAX1183 data sheet for 40Msps. In addition to these speed grades, this family includes a 20Msps multiplexed output version (MAX1185), for which digital data is presented time-interleaved on a single, parallel 10-bit output port.
Features
o Single +3V Operation o Excellent Dynamic Performance: 59.5dB SNR at fIN = 7.5MHz 74dB SFDR at fIN = 7.5MHz o Low Power: 35mA (Normal Operation) 2.8mA (Sleep Mode) 1A (Shutdown Mode) o 0.02dB Gain and 0.25 Phase Matching (typ) o Wide 1Vp-p Differential Analog Input Voltage Range o 400MHz -3dB Input Bandwidth o On-Chip +2.048V Precision Bandgap Reference o User-Selectable Output Format--Two's Complement or Offset Binary o 48-Pin TQFP Package with Exposed Pad for Improved Thermal Dissipation o Evaluation Kit Available
MAX1184
Ordering Information
PART MAX1184ECM TEMP. RANGE -40C to +85C PIN-PACKAGE 48 TQFP-EP
Pin Configuration
REFN REFP REFIN REFOUT D9A D8A D7A D6A D5A D4A D3A D2A
48 47 46 45 44 43 42 41 40 39 38
COM VDD GND INA+ INAVDD GND INBINB+ GND VDD CLK
37
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
36 35 34 33 32 31 30 29 28 27 26 25
D1A D0A OGND OVDD OVDD OGND D0B D1B D2B D3B D4B D5B
Applications
High Resolution Imaging I/Q Channel Digitization Multchannel IF Undersampling Instrumentation Video Application
MAX1184
________________________________________________________________ Maxim Integrated Products
GND T/B SLEEP PD OE D9B D8B D7B D6B
GND VDD VDD
48 TQFP-EP
1
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Dual 10-Bit, 20Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1184
ABSOLUTE MAXIMUM RATINGS
VDD, OVDD to GND...............................................-0.3V to +3.6V OGND to GND.......................................................-0.3V to +0.3V INA+, INA-, INB+, INB- to GND ...............................-0.3V to VDD REFIN, REFOUT, REFP, REFN, CLK, COM to GND ..........................................-0.3V to (VDD + 0.3V) OE, PD, SLEEP, T/B, D9A-D0A, D9B-D0B to OGND .............................-0.3V to (OVDD + 0.3V) Continuous Power Dissipation (TA = +70C) 48-Pin TQFP (derate 12.5mW/C above +70C).......1000mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +3V, OVDD = +2.5V, 0.1F and 1.0F capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k resistor, VIN = 2Vp-p (differential w.r.t. COM), CL = 10pF at digital outputs (Note 5), fCLK = 20MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error ANALOG INPUT Differential Input Voltage Range Common-Mode Input Voltage Range Input Resistance Input Capacitance CONVERSION RATE Maximum Clock Frequency Data Latency DYNAMIC CHARACTERISTICS (fCLK = 20MHz, 4096-point FFT) Signal-to-Noise Ratio Signal-to-Noise and Distortion Spurious-Free Dynamic Range SNR SINAD SFDR fINA or B = 7.5MHz, TA = +25C fINA or B = 12MHz fINA or B = 7.5MHz, TA = +25C fINA or B = 12MHz fINA or B = 7.5MHz, TA = +25C fINA or B = 12MHz 64 57 57.3 59.5 59.4 59.4 59.2 74 72 dB dB dBc fCLK 20 5 MHz Clock Cycles VDIFF VCM RIN CIN Switched capacitor load Differential or single-ended inputs 1.0 VDD/2 0.5 100 5 V V k pF INL DNL fIN = 7.5MHz fIN = 7.5MHz, no missing codes guaranteed 10 0.5 0.25 < 1 0 1.5 1.0 1.7 2 Bits LSB LSB % FS % FS SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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Dual 10-Bit, 20Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +3V, OVDD = +2.5V, 0.1F and 1.0F capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k resistor, VIN = 2Vp-p (differential w.r.t. COM), CL = 10pF at digital outputs (Note 5), fCLK = 20MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Third-Harmonic Distortion Intermodulation Distortion Total Harmonic Distortion (first 4 harmonics) Small-Signal Bandwidth Full-Power Bandwidth Aperture Delay Aperture Jitter Overdrive Recovery Time Differential Gain Differential Phase Output Noise INTERNAL REFERENCE Reference Output Voltage Reference Temperature Coefficient Load Regulation BUFFERED EXTERNAL REFERENCE (VREFIN = +2.048V) REFIN Input Voltage Positive Reference Output Voltage Negative Reference Output Voltage Differential Reference Output Voltage Range REFIN Resistance VREFIN VREFP VREFN VREF RREFIN VREF = VREFP - VREFN 0.98 2.048 2.012 0.988 1.024 >50 1.07 V V V V M REFOUT TCREF 2.048 3% 60 1.25 V ppm/C mV/mA INA+ = INA- = INB+ = INB- = COM FPBW tAD tAJ For 1.5 full-scale input SYMBOL HD3 IMD THD CONDITIONS fINA or B = 7.5MHz fINA or B = 12MHz fINA or B = 11.985MHz at -6.5dB FS fINA or B = 12.893MHz at -6.5dB FS (Note 2) fINA or B = 7.5MHz, TA = +25C fINA or B = 12MHz Input at -20dB FS, differential inputs Input at -0.5dB FS, differential inputs MIN TYP -74 -72 -76 -72 -71 500 400 1 2 2 1 0.25 0.2 -64 MAX UNITS dBc dBc dBc MHz MHz ns psRMS ns % degrees LSBRMS
MAX1184
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3
Dual 10-Bit, 20Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1184
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +3V, OVDD = +2.5V, 0.1F and 1.0F capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k resistor, VIN = 2Vp-p (differential w.r.t. COM), CL = 10pF at digital outputs (Note 5), fCLK = 20MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Maximum REFP, COM Source Current Maximum REFP, COM Sink Current Maximum REFN Source Current Maximum REFN Sink Current SYMBOL ISOURCE ISINK ISOURCE ISINK RREFP, RREFN VREF VCOM VREFP VREFN Measured between REFP and COM, and REFN and COM VREF = VREFP - VREFN CONDITIONS MIN TYP 5 -250 250 -5 MAX UNITS mA A A mA
UNBUFFERED EXTERNAL REFERENCE (VREFIN = AGND, reference voltage applied to REFP, REFN, and COM) REFP, REFN Input Resistance Differential Reference Input Voltage COM Input Voltage REFP Input Voltage REFN Input Voltage 4 1.024 10% VDD/2 10% VCOM + VREF /2 VCOM VREF /2 CLK PD, OE, SLEEP, T/B CLK PD, OE, SLEEP, T/B 0.1 VIH = OVDD or VDD (CLK) VIL = 0 5 ISINK = 200A ISOURCE = 200A OE = OVDD OE = OVDD 5 OVDD - 0.2 10 0.2 5 5 0.8 VDD 0.8 OVDD 0.2 VDD 0.2 OVDD k V V V V
DIGITAL INPUTS (CLK, PD, OE, SLEEP, T/B) Input High Threshold Input Low Threshold Input Hysteresis Input Leakage Input Capacitance Output Voltage Low Output Voltage High Three-State Leakage Current Three-State Output Capacitance VIH VIL VHYST IIH IIL CIN VOL VOH ILEAK COUT V V V A pF V V A pF
DIGITAL OUTPUTS (D9A-D0A, D9B-D0B)
4
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Dual 10-Bit, 20Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1184
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +3V, OVDD = +2.5V, 0.1F and 1.0F capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k resistor, VIN = 2Vp-p (differential w.r.t. COM), CL = 10pF at digital outputs (Note 5), fCLK = 20MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER POWER REQUIREMENTS Analog Supply Voltage Range Output Supply Voltage Range Analog Supply Current VDD OVDD Operating, fINA or B = 7.5MHz at -0.5dB FS IVDD Sleep mode Shutdown, clock idle, PD = OE = OVDD Operating, CL = 15pF, fINA or B = 7.5MHz at -0.5dB FS Output Supply Current IOVDD Sleep mode Shutdown, clock idle, PD = OE = OVDD Operating, fINA or B = 7.5MHz at -0.5dB FS Power Dissipation PDISS Sleep mode Shutdown, clock idle, PD = OE = OVDD Power-Supply Rejection Ratio TIMING CHARACTERISTICS CLK Rise to Output Data Valid Output Enable Time Output Disable Time CLK Pulse Width High CLK Pulse Width Low Wake-Up Time tDO tENABLE tDISABLE tCH tCL tWAKE Figure 3 (Note 3) Figure 4 Figure 4 Figure 3, clock period: 50ns Figure 3, clock period: 50ns Wakeup from sleep mode (Note 4) Wakeup from shutdown (Note 4) fINA or B = 7.5MHz at -0.5dB FS fINA or B = 7.5MHz at -0.5dB FS fINA or B = 7.5MHz at -0.5dB FS 5 10 1.5 25 7.5 25 7.5 0.51 1.5 -70 0.02 0.25 0.2 8 ns ns ns ns ns s PSRR Offset Gain 2.7 1.7 3.0 2.5 35 2.8 1 3.8 100 2 105 8.4 3 0.2 0.1 45 10 150 15 3.6 3.6 50 V V mA A mA A mW W mV/V %/V SYMBOL CONDITIONS MIN TYP MAX UNITS
CHANNEL-TO-CHANNEL MATCHING Crosstalk Gain Matching Phase Matching dB dB degrees
Note 1: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dB FS referenced to a +1.024V full-scale input voltage range. Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is 6dB or better, if referenced to the two-tone envelope. Note 3: Digital outputs settle to VIH, VIL. Parameter guaranteed by design. Note 4: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down. Note 5: Equivalent dynamic performance is obtainable over full OVDD range with reduced CL.
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5
Dual 10-Bit, 20Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1184
Typical Operating Characteristics
(VDD = +3V, OVDD = +2.5V, VREFIN = +2.048V, differential input at -0.5dB FS, fCLK = 20MHz, CL 10pF, TA = +25C, unless otherwise noted.)
FFT PLOT CHA (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)
MAX1184 toc01
FFT PLOT CHB (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)
MAX1184 toc02
FFT PLOT CHA (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)
-10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 HD3 HD2 fCLK = 20.0005678MHz fINA = 7.5343935MHz fINB = 11.9852035MHz AINA = -0.489dB FS CHA
MAX1184 toc03
0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 0 1 2 3 4 5 6 7 8 9 HD3 HD2 fCLK = 20.0005678MHz fINA = 5.9742906MHz fINB = 7.5343935MHz AINA = -0.525dB FS CHA
0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 HD3 HD2 fCLK = 20.0005678MHz fINA = 5.9742906MHz fINB = 7.5243935MHz AINB = -0.462dB FS CHB
0
10
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
FFT PLOT CHB (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)
MAX1184 toc04
TWO-TONE IMD PLOT DIFFERENTIAL INPUT, 8192-POINT DATA RECORD
MAX1184 toc05
SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY
CHB 60
MAX1184 toc06
0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 0 1 2 3 4 5 6 7 8 9 HD3 HD2 fCLK = 20.0005678MHz fINA = 7.5343935MHz fINB = 11.9852035MHz AINB = -0.471dB FS CHB
0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 IMD3 IMD2 IMD3 fCLK = 20.0005678MHz fIN1 = 11.9852035MHz fIN2 = 12.8934324MHz AIN = -6.5dB FS TWO-TONE ENVELOPE = -0.498dB FS fIN2
61
fIN1
SNR (dB)
59
CHA
58
57
56 0 2 4 6 8 10 12 14 16 18 20 1 10 ANALOG INPUT FREQUENCY (MHz) 100 ANALOG INPUT FREQUENCY (MHz)
10
ANALOG INPUT FREQUENCY (MHz)
SIGNAL-TO-NOISE + DISTORTION vs. ANALOG INPUT FREQUECNY
MAX1184 toc07
TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY
MAX1184 toc08
SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY
MAX1184 toc09
61 CHB
-63 -65 -67 THD (dBc)
80 CHA
60
76 SFDR (dBc)
SINAD (dB)
59
CHA
-69 -71 -73
CHB
72
58
68
CHB
CHA 64
57 -75 56 1 10 ANALOG INPUT FREQUENCY (MHz) 100 -77 1 10 ANALOG INPUT FREQUENCY (MHz) 100
60 1 10 ANALOG INPUT FREQUENCY (MHz) 100
6
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Dual 10-Bit, 20Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1184
Typical Operating Characteristics (continued)
(VDD = +3V, OVDD = +2.5V, VREFIN = +2.048V, differential input at -0.5dB FS, fCLK = 20MHz, CL 10pF, TA = +25C, unless otherwise noted.)
FULL-POWER INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY, SINGLE-ENDED
MAX1184 toc10
SMALL-SIGNAL INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY, SINGLE-ENDED
MAX1184 toc11
SIGNAL-TO-NOISE RATIO vs. INPUT POWER (fIN = 7.5343935MHz)
MAX1184 toc12
6 4 2 GAIN (dB)
6 VIN = 100mVP-P 4 2 GAIN (dB) 0 -2 -4 -6 -8
65 60 55 SNR (dB) 50 45 40 35
0 -2 -4 -6 -8 1 10 100 1000 ANALOG INPUT FREQUENCY (MHz)
1
10
100
1000
-20
-16
-12
-8
-4
0
ANALOG INPUT FREQUENCY (MHz)
INPUT POWER (dB FS)
SIGNAL-TO-NOISE + DISTORTION vs. INPUT POWER (fIN = 7.5343935MHz)
MAX1184 toc13
TOTAL HARMONIC DISTORTION vs. INPUT POWER (fIN = 7.5343935MHz)
MAX1184 toc14
SPURIOUS-FREE DYNAMIC RANGE vs. INPUT POWER (fIN = 7.5343935MHz)
MAX1184 toc15
65 60 55 SINAD (dB)
-58
100 90 80
-62
THD (dBc)
-66
SFDR (dBc)
50 45 40 35 -20 -16 -12 -8 -4 0 INPUT POWER (dB FS)
70 60
-70
-74
50 40 -20 -16 -12 -8 -4 0 -20 -16 -12 -8 -4 0 INPUT POWER (dB FS) INPUT POWER (dB FS)
-78
INTEGRAL NONLINEARITY (BEST END-POINT FIT)
MAX1184 toc16
DIFFERENTIAL NONLINEARITY
MAX1184 toc17
GAIN ERROR vs. TEMPERATURE
MAX1184 toc18
0.3 0.2 0.1
0.3 0.2 0.1 DNL (LSB) 0 -0.1 -0.2 -0.3
0.6 0.5 GAIN ERROR (%FS) 0.4 0.3 0.2 0.1 0 -0.1
INL (LSB)
0 -0.1 -0.2 -0.3 0 128 256 384 512 640 768 896 1024 DIGITAL OUTPUT CODE
CHB
CHA -40 -15 10 35 60 85
0
128 256 384 512 640 768 896 1024 DIGITAL OUTPUT CODE
TEMPERATURE (C)
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7
Dual 10-Bit, 20Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1184
Typical Operating Characteristics (continued)
(VDD = +3V, OVDD = +2.5V, VREFIN = +2.048V, differential input at -0.5dB FS, fCLK = 20MHz, CL 10pF, TA = +25C, unless otherwise noted.)
OFFSET ERROR vs. TEMPERATURE
MAX1184 toc19
ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE
MAX1184 toc20
0.1
36
0 OFFSET ERROR (%FS)
35
-0.1 CHB -0.2
IVDD (mA)
34
33
-0.3 CHA -0.4 -40 -15 10 35 60 85 TEMPERATURE (C)
32
31 2.70 2.85 3.00 3.15 VDD (V) 3.30 3.45 3.60
ANALOG SUPPLY CURRENT vs. TEMPERATURE
MAX1184 toc21
ANALOG POWER-DOWN CURRENT vs. ANALOG POWER SUPPLY
OE = PD = OVDD 0.16
MAX1184 toc22
38
0.20
36
IVDD (mA)
IVDD (A)
34
0.12
32
0.08
30
0.04
28 -40 -15 10 35 60 85 TEMPERATURE (C)
0 2.70 2.85 3.00 3.15 VDD (V) 3.30 3.45 3.60
SFDR, SNR, THD, SINAD vs. CLOCK DUTY CYCLE
MAX1184 toc23
INTERNAL REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE
MAX1184 toc24
80 SFDR SFDR, SNR, THD, SINAD (dB) 74
fIN = 7.5343935MHz
2.0090
2.0080 VREFOUT (V)
68 SNR 62
THD
2.0070
2.0060
56
SINAD
2.0050
50 30 35 40 45 50 55 60 65 70 CLOCK DUTY CYCLE (%)
2.0040 2.70 2.85 3.00 3.15 VDD (V) 3.30 3.45 3.60
8
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Dual 10-Bit, 20Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs
Typical Operating Characteristics (continued)
(VDD = +3V, OVDD = +2.5V, VREFIN = +2.048V, differential input at -0.5dB FS, fCLK = 20MHz, CL 10pF, TA = +25C, unless otherwise noted.)
INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE
MAX1184 toc25
MAX1184
OUTPUT NOISE HISTOGRAM (DC INPUT)
63,000 56,000 49,000 64,515
MAX1184 toc26
2.015
70,000
2.010
VREOUT (V)
COUNTS
2.005
42,000 35,000 28,000 21,000
2.000
1.995
14,000 7,000
-40 -15 10 35 60 85
1.990 TEMPERATURE (C)
0
0 N-2
869 N-1 N
152 N+1
0 N+2
DIGITAL OUTPUT CODE
Pin Description
PIN 1 2, 6, 11, 14, 15 3, 7, 10, 13, 16 4 5 8 9 12 17 NAME COM VDD GND INA+ INAINBINB+ CLK T/B FUNCTION Common-Mode Voltage Input/Output. Bypass to GND with a 0.1F capacitor. Analog Supply Voltage. Bypass to GND with a capacitor combination of 2.2F in parallel with 0.1F. Analog Ground Channel A Positive Analog Input. For single-ended operation, connect signal source to INA+. Channel A Negative Analog Input. For single-ended operation, connect INA- to COM. Channel B Negative Analog Input. For single-ended operation, connect INB- to COM. Channel B Positive Analog Input. For single-ended operation, connect signal source to INB+. Converter Clock Input T/B selects the ADC digital output format. High: Two's complement. Low: Straight offset binary. Sleep Mode Input. High: Deactivates the two ADCs, but leaves the reference bias circuit active. Low: Normal operation. Power-Down Input. High: Power-down mode Low: Normal operation Output Enable Input. High: Digital outputs disabled Low: Digital outputs enabled
18
SLEEP
19
PD
20
OE
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Dual 10-Bit, 20Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1184
Pin Description (continued)
PIN 21 22 23 24 25 26 27 28 29 30 31, 34 32, 33 35 36 37 38 39 40 41 42 43 44 45 46 47 48 NAME D9B D8B D7B D6B D5B D4B D3B D2B D1B D0B OGND OVDD D0A D1A D2A D3A D4A D5A D6A D7A D8A D9A REFOUT REFIN REFP REFN FUNCTION Three-State Digital Output, Bit 9 (MSB), Channel B Three-State Digital Output, Bit 8, Channel B Three-State Digital Output, Bit 7, Channel B Three-State Digital Output, Bit 6, Channel B Three-State Digital Output, Bit 5, Channel B Three-State Digital Output, Bit 4, Channel B Three-State Digital Output, Bit 3, Channel B Three-State Digital Output, Bit 2, Channel B Three-State Digital Output, Bit 1, Channel B Three-State Digital Output, Bit 0 (LSB), Channel B Output Driver Ground Output Driver Supply Voltage. Bypass to OGND with a capacitor combination of 2.2F in parallel with 0.1F. Three-State Digital Output, Bit 0 (LSB), Channel A Three-State Digital Output, Bit 1, Channel A Three-State Digital Output, Bit 2, Channel A Three-State Digital Output, Bit 3, Channel A Three-State Digital Output, Bit 4, Channel A Three-State Digital Output, Bit 5, Channel A Three-State Digital Output, Bit 6, Channel A Three-State Digital Output, Bit 7, Channel A Three-State Digital Output, Bit 8, Channel A Three-State Digital Output, Bit 9 (MSB), Channel A Internal Reference Voltage Output. May be connected to REFIN through a resistor or a resistor divider. Reference Input. VREFIN = 2 (VREFP - VREFN). Bypass to GND with a >1nF capacitor. Positive Reference Input/Output. Conversion range is (VREFP - VREFN). Bypass to GND with a > 0.1F capacitor. Negative Reference Input/Output. Conversion range is (VREFP - VREFN). Bypass to GND with a > 0.1F capacitor.
10
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Dual 10-Bit, 20Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs
Detailed Description
The MAX1184 uses a 9-stage, fully-differential pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half clock cycle. Counting the delay through the output latch, the clockcycle latency is five clock cycles. 1.5-bit (2-comparator) flash ADCs convert the heldinput voltages into a digital code. The digital-to-analog converters (DACs) convert the digitized results back into analog voltages, which are then subtracted from the original held input signals. The resulting error signals are then multiplied by two and the residues are passed along to the next pipeline stages, where the process is repeated until the signals have been processed by all nine stages. Digital error correction compensates for ADC comparator offsets in each of these pipeline stages and ensures no missing codes. hold mode. In track mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b are closed. The fully differential circuits sample the input signals onto the two capacitors (C2a and C2b) through switches S4a and S4b. S2a and S2b set the common mode for the amplifier input, and open simultaneously with S1, sampling the input waveform. Switches S4a and S4b are then opened before switches S3a and S3b, connect capacitors C1a and C1b to the output of the amplifier, and switch S4c is closed. The resulting differential voltages are held on capacitors C2a and C2b. The amplifiers are used to charge capacitors C1a and C1b to the same values originally held on C2a and C2b. These values are then presented to the first-stage quantizers and isolate the pipelines from the fast-changing inputs. The wide input bandwidth T/H amplifiers allow the MAX1184 to trackand-sample/hold analog inputs of high frequencies (> Nyquist). The ADC inputs (INA+, INB+, INA-, and INB-) can be driven either differentially or single-ended. Match the impedance of INA+ and INA-, as well as INB+ and INB- and set the common-mode voltage to midsupply (VDD/2) for optimum performance.
MAX1184
Input Track-and-Hold (T/H) Circuits
Figure 2 displays a simplified functional diagram of the input track-and-hold (T/H) circuits in both track-and-
T/H
x2
VOUT
VIN
T/H
x2
VOUT
FLASH ADC 1.5 BITS
DAC
FLASH ADC 1.5 BITS
DAC
2-BIT FLASH ADC STAGE 1 STAGE 2 STAGE 8 STAGE 9 STAGE 1 STAGE 2 STAGE 8
2-BIT FLASH ADC STAGE 9
DIGITAL CORRECTION LOGIC T/H 10 D9B-D0B T/H
DIGITAL CORRECTION LOGIC 10 D9B-D0B
VINB
VINB
VINA = INPUT VOLTAGE BETWEEN INA+ AND INA- (DIFFERENTIAL OR SINGLE-ENDED) VINB = INPUT VOLTAGE BETWEEN INB+ AND INB- (DIFFERENTIAL OR SINGLE-ENDED)
Figure 1. Pipelined Architecture--Stage Blocks ______________________________________________________________________________________ 11
Dual 10-Bit, 20Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1184
INTERNAL BIAS S2a C1a S4a INA+ C2a S4c S1 OUT S4b C2b C1b S3b S2b INTERNAL BIAS S5b COM HOLD INTERNAL BIAS S2a C1a S4a INB+ C2a S4c S1 OUT S4b C2b C1b S3b S2b INTERNAL BIAS S5b COM MAX1184 OUT TRACK HOLD TRACK CLK INTERNAL NONOVERLAPPING CLOCK SIGNALS OUT COM S5a S3a
INA-
COM S5a S3a
INB-
Figure 2. MAX1184 T/H Amplifiers
12
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Dual 10-Bit, 20Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs
Analog Inputs and Reference Configurations
The full-scale range of the MAX1184 is determined by the internally generated voltage difference between REFP (VDD/2 + VREFIN/4) and REFN (VDD/2 - VREFIN/4). The full-scale range for both on-chip ADCs is adjustable through the REFIN pin, which is provided for this purpose. REFOUT, REFP, COM (VDD/2), and REFN are internally buffered low-impedance outputs. The MAX1184 provides three modes of reference operation: * Internal reference mode * Buffered external reference mode * Unbuffered external reference mode In internal reference mode, connect the internal reference output REFOUT to REFIN through a resistor (e.g., 10k) or resistor-divider, if an application requires a reduced full-scale range. For stability and noise filtering purposes, bypass REFIN with a >10nF capacitor to GND. In internal reference mode, REFOUT, COM, REFP, and REFN become low-impedance outputs. In buffered external reference mode, adjust the reference voltage levels externally by applying a stable and accurate voltage at REFIN. In this mode, COM, REFP, and REFN become outputs. REFOUT may be left open or connected to REFIN through a >10k resistor. In unbuffered external reference mode, connect REFIN to GND. This deactivates the on-chip reference buffers for REFP, COM, and REFN. With their buffers shut down, these nodes become high impedance and may be driven through separate external reference sources. ered as an analog input and routed away from any analog input or other digital signal lines. The MAX1184 clock input operates with a voltage threshold set to VDD/2. Clock inputs with a duty cycle other than 50%, must meet the specifications for high and low periods as stated in the Electrical Characteristics.
MAX1184
System Timing Requirements
Figure 3 depicts the relationship between the clock input, analog input, and data output. The MAX1184 samples at the rising edge of the input clock. Output data for channels A and B is valid on the next rising edge of the input clock. The output data has an internal latency of five clock cycles. Figure 4 also determines the relationship between the input clock parameters and the valid output data on channels A and B.
Digital Output Data, Output Data Format Selection (T/B), Output Enable (OE)
All digital outputs, D0A-D9A (Channel A) and D0B-D9B (Channel B), are TTL/CMOS logic-compatible. There is a 5-clock-cycle latency between any particular sample and its corresponding output data. The output coding can be chosen to be either straight offset binary or two's complement (Table 1) controlled by a single pin (T/B). Pull T/B low to select offset binary and high to activate two's complement output coding. The capacitive load on the digital outputs D0A-D9A and D0B-D9B should be kept as low as possible (<15pF), to avoid large digital currents that could feed back into the analog portion of the MAX1184, thereby degrading its dynamic performance. Using buffers on the digital outputs of the ADCs can further isolate the digital outputs from heavy capacitive loads. To further improve the dynamic performance of the MAX1184 small-series resistors (e.g., 100) may be added to the digital output paths close to the MAX1184. Figure 4 displays the timing relationship between output enable and data output valid as well as powerdown/wake-up and data output valid.
Clock Input (CLK)
The MAX1184's CLK input accepts CMOS-compatible clock signals. Since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (< 2ns). In particular, sampling occurs on the rising edge of the clock signal, requiring this edge to provide lowest possible jitter. Any significant aperture jitter would limit the SNR performance of the on-chip ADCs as follows: SNRdB = 20 log10 (1 / [2 x fIN x tAJ]), where fIN represents the analog input frequency and tAJ is the time of the aperture jitter. Clock jitter is especially critical for undersampling applications. The clock input should always be consid-
Power-Down (PD) and Sleep (SLEEP) Modes
The MAX1184 offers two power-save modes--sleep and full power-down mode. In sleep mode (SLEEP = 1), only the reference bias circuit is active (both ADCs are disabled), and current consumption is reduced to 2.8mA. To enter full power-down mode, pull PD high. With OE simultaneously low, all outputs are latched at the last value prior to the power down. Pulling OE high forces the digital outputs into a high-impedance state.
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13
Dual 10-Bit, 20Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1184
5 CLOCK-CYCLE LATENCY N N+1 N+2 N+3 N+4 N+5 N+6
ANALOG INPUT
CLOCK INPUT tDO DATA OUTPUT D9A-D0A N-6 N-5 N-4 tCH N-3
tCL N-2 N-1 N N+1
DATA OUTPUT D9B-D0B
N-6
N-5
N-4
N-3
N-2
N-1
N
N+1
Figure 3. System Timing Diagram
OE
tENABLE OUTPUT D9A-D0A HIGH-Z
tDISABLE HIGH-Z
amplifiers. The user may select the RISO and CIN values to optimize the filter performance, to suit a particular application. For the application in Figure 5, a RISO of 50 is placed before the capacitive load to prevent ringing and oscillation. The 22pF CIN capacitor acts as a small bypassing capacitor.
VALID DATA
Using Transformer Coupling
A RF transformer (Figure 6) provides an excellent solution to convert a single-ended source signal to a fully differential signal, required by the MAX1184 for optimum performance. Connecting the center tap of the transformer to COM provides a VDD/2 DC level shift to the input. Although a 1:1 transformer is shown, a stepup transformer may be selected to reduce the drive requirements. A reduced signal swing from the input driver, such as an op amp, may also improve the overall distortion. In general, the MAX1184 provides better SFDR and THD with fully-differential input signals than singleended drive, especially for very high input frequencies. In differential input mode, even-order harmonics are lower as both inputs (INA+, INA- and/or INB+, INB-) are balanced, and each of the ADC inputs only requires
OUTPUT D9B-D0B
HIGH-Z
VALID DATA
HIGH-Z
Figure 4. Output Timing Diagram
Applications Information
Figure 5 depicts a typical application circuit containing two single-ended to differential converters. The internal reference provides a V DD/2 output voltage for level shifting purposes. The input is buffered and then split to a voltage follower and inverter. One lowpass filter per ADC suppresses some of the wideband noise associated with high-speed operational amplifiers follows the
14
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Dual 10-Bit, 20Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1184
Table 1. MAX1184 Output Codes For Differential Inputs
DIFFERENTIAL INPUT VOLTAGE* VREF x 511/512 VREF x 1/512 0 - VREF x 1/512 -VREF x 511/512 -VREF x 512/512 *VREF = VREFP - VREFN DIFFERENTIAL INPUT +FULL SCALE - 1LSB + 1 LSB Bipolar Zero - 1 LSB - FULL SCALE + 1 LSB - FULL SCALE STRAIGHT OFFSET BINARY T/B = 0 11 1111 1111 10 0000 0001 10 0000 0000 01 1111 1111 00 0000 0001 00 0000 0000 TWO'S COMPLEMENT T/B = 1 01 1111 1111 00 0000 0001 00 0000 0000 11 1111 1111 10 0000 0001 10 0000 0000
half the signal swing compared to a single-ended mode.
Grounding, Bypassing, and Board Layout
The MAX1184 requires high-speed board layout design techniques. Locate all bypass capacitors as close to the device as possible, preferably on the same side as the ADC, using surface-mount devices for minimum inductance. Bypass VDD, REFP, REFN, and COM with two parallel 0.1F ceramic capacitors and a 2.2F bipolar capacitor to GND. Follow the same rules to bypass the digital supply (OVDD) to OGND. Multilayer boards with separated ground and power planes produce the highest level of signal integrity. Consider the use of a split ground plane arranged to match the physical location of the analog ground (GND) and the digital output driver ground (OGND) on the ADCs package. The two ground planes should be joined at a single point such that the noisy digital ground currents do not interfere with the analog ground plane. The ideal location of this connection can be determined experimentally at a point along the gap between the two ground planes, which produces optimum results. Make this connection with a low-value, surface-mount resistor (1 to 5), a ferrite bead, or a direct short. Alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy, digital systems ground plane (e.g., downstream output buffer or DSP ground plane). Route high-speed digital signal traces away from the sensitive analog traces of either channel. Make sure to isolate the analog input lines to each respective converter to minimize channelto-channel crosstalk. Keep all signal lines short and free of 90 degree turns.
Single-Ended AC-Coupled Input Signal
Figure 7 shows an AC-coupled, single-ended application. Amplifiers like the MAX4108 provide high-speed, high-bandwidth, low noise, and low distortion to maintain the integrity of the input signal.
Typical QAM Demodulation Application
The most frequently used modulation technique for digital communications applications is probably the Quadrature Amplitude Modulation (QAM). Typically found in spread-spectrum based systems, a QAM signal represents a carrier frequency modulated in both amplitude and phase. At the transmitter, modulating the baseband signal with quadrature outputs, a local oscillator followed by subsequent up-conversion can generate the QAM signal. The result is an in-phase (I) and a quadrature (Q) carrier component, where the Q component is 90 degree phase-shifted with respect to the inphase component. At the receiver, the QAM signal is divided down into it's I and Q components, essentially representing the modulation process reversed. Figure 8 displays the demodulation process performed in the analog domain, using the dual matched +3V, 10-bit ADC (MAX1184), and the MAX2451 quadrature demodulator to recover and digitize the I and Q baseband signals. Before being digitized by the MAX1184, the mixed down-signal components may be filtered by matched analog filters, such as Nyquist or pulse-shaping filters which remove any unwanted images from the mixing process, thereby enhancing the overall signal-to-noise (SNR) performance and minimizing intersymbol interference.
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15
Dual 10-Bit, 20Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1184
+5V
0.1F LOWPASS FILTER MAX4108 300 0.1F INA+ RIS0 50 CIN 22pF
-5V
0.1F
600 300 600 COM +5V 0.1F +5V 0.1F INPUT 0.1F MAX4108 300 0.1F MAX4108 INARIS0 50 0.1F CIN 22pF LOWPASS FILTER 600
-5V
300 -5V
300 300 +5V 600
MAX1184
0.1F LOWPASS FILTER MAX4108 300 0.1F INB+ RIS0 50 CIN 22pF
-5V
0.1F
600 300 600
+5V
0.1F +5V 0.1F 600 0.1F LOWPASS FILTER INBRIS0 50 -5V 0.1F CIN 22pF
INPUT MAX4108 300 0.1F MAX4108
-5V
300
300 300 600
Figure 5. Typical Application for Single-Ended to Differential Conversion 16 ______________________________________________________________________________________
Dual 10-Bit, 20Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1184
25 INA+ 22pF 0.1F VIN N.C. 1 2 3 T1 6 5 4 2.2F 0.1F
COM
MINICIRCUITS TT1-6 25 INA22pF MAX1184 25 INB+ 22pF 0.1F VIN N.C. 1 2 3 T1 6 5 4 2.2F 0.1F
MINICIRCUITS TT1-6 25 INB22pF
Figure 6. Transformer-Coupled Input Drive
Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX1184 are measured using the best straight-line fit method.
error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function.
Dynamic Parameter Definitions
Aperture Jitter
Figure 9 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay.
Aperture Delay
Aperture delay (tAD) is the time defined between the falling edge of the sampling clock and the instant when an actual sample is taken (Figure 9).
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an actual step-width and the ideal value of 1LSB. A DNL
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17
Dual 10-Bit, 20Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1184
REFP
VIN MAX4108 100
0.1F
1k RISO 50 INA+ 1k CIN 22pF COM REFN 0.1F RISO 50 INACIN 22pF REFP
100
MAX1184
VIN MAX4108 100
0.1F
1k RISO 50 INB+ 1k CIN 22pF
REFN
0.1F
RISO 50 INBCIN 22pF
100
Figure 7: Using an Op Amp for Single-Ended, AC-Coupled Input Drive
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC's resolution (N-Bits): SNRdB[max] = 6.02dB x N + 1.76dB In reality, there are other noise sources besides quantization noise e.g. thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset.
18
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal to all spectral components minus the fundamental and the DC offset.
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC error consists of quantization noise only. ENOB is computed from: ENOB = SINADdB - 1.76dB 6.02dB
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Dual 10-Bit, 20Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1184
MAX2451
INA+ INA0 90
MAX1184 INB+ INB-
DSP POST PROCESSING
DOWNCONVERTER /8
Figure 8. Typical QAM Application, Using the MAX1184
Total Harmonic Distortion (THD)
CLK
THD is typically the ratio of the RMS sum of the first four harmonics of the input signal to the fundamental itself. This is expressed as: V2 2 + V3 2 + V4 2 + V5 2 THD = 20 x log10 V1 where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics.
TRACK HOLD TRACK
ANALOG INPUT tAD tAJ SAMPLED DATA (T/H)
T/H
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset.
Figure 9. T/H Aperture Timing
Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in decibels of either input tone to the worst 3rd-order (or higher) intermodulation products. The individual input tone levels are at -6.5dB full scale and their envelope is at -0.5dB full scale.
Chip Information
TRANSISTOR COUNT: 10,811 PROCESS: CMOS
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19
Dual 10-Bit, 20Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1184
Functional Diagram
VDD GND INA+ T/H INAPIPELINE ADC 10 DEC OUTPUT DRIVERS 10 D9A-D0A OGND OVDD
CLK
CONTROL OE
INB+ T/H INB-
PIPELINE ADC
10 DEC
OUTPUT DRIVERS
10 D9B-D0B
REFERENCE
MAX1184
REFOUT REFN COM REFP REFIN
T/B PD SLEEP
20
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Dual 10-Bit, 20Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs
Package Information
48L,TQFP.EPS
MAX1184
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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